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integrated circuit systems, inc. 1186g?04/16/07 ICSSSTUB32871A recommended application: ? ddr2 memory modules ? provides complete ddr dimm solution with ics98ulpa877a, ics97ulp877, or idtcspua877a ? optimized for ddr2 400/533/667 jedec 4 rank vlp dimms product features: ? 27-bit 1:1 registered buffer with parity check functionality ? supports sstl_18 jedec specification on data inputs and outputs ? supports lvcmos switching levels on reset input ? 50% more dynamic driver strength than standard sstu32864 ? low voltage operation v dd = 1.7v to 1.9v ? available in 96 bga package 27-bit registered buffer for ddr2 functionality truth table pin configuration 96 ball bga (top view) a b 123456 c d e f g h j k l m n p r t in puts outputs reset dcs0 dcs1 csgate enable ck ck dn, dodtn, dcken qn qcs qodt, qcke h llx ll l l h llx hh l h h l l x l or h l or h x q 0 q 0 q 0 h lhx ll l l h lhx hh l h h l h x l or h l or h x q 0 q 0 q 0 h hlx ll h l h hlx hh h h h h l x l or h l or h x q 0 q 0 q 0 h hhl llhl h hhl hhhh h h h l l or h l or h l or h l or h x x q 0 q 0 q 0 hhhh l q 0 hl hhhh h q 0 hh hhhh q 0 q 0 q 0 l x or floating x or floating x or floating x or floating x or floating x or floating lll
2 1186g?04/16/07 ICSSSTUB32871A ball assignments 27 bit 1:1 register a dcke0 d0 csgateen v dd qcke0 qcke1 b d1 gnd gnd q0 q1 c d2 dodt1 v dd v dd q2 dnu d dodt0 ptyerr gnd gnd qodt0 qodt1 e d3 d4 v dd v dd q3 q4 f d5 d6 gnd gnd q5 q6 g par_in reset v dd v dd nc nc h ck dcs0 gnd gnd qcs0 qcs1 j ck dcs1 v dd v dd nc nc k d7 d8 gnd gnd q7 q8 l d 9 d10 v dd v dd q 9 q10 m d11 d12 gnd gnd q11 q12 n d13 d14 v dd v dd q13 q14 p d15 d16 gnd gnd q15 q16 r d17 d18 v dd v dd q17 q18 t d1 9 d20 v dd q1 9 q20 123456 dcke1 v ref
3 1186g?04/16/07 ICSSSTUB32871A general description this 27-bit 1:1 registered buffer with parity is designed for 1.7v to 1.9v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8 v cmos drivers that have been optimized to drive the ddr2 dimm load. the ICSSSTUB32871A operates from a differential clock (ck and ck). data are registered at the crossing of ck going high, and ck going low. the device supports low-power standby operation. when the reset input (reset) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (vref) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs except ptyerr are forced low. the lvcmos reset input must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr2 rdimm application, reset is specified to be completely asynchronous with respect to ck and ck. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the ICSSSTUB32871A must ensure that the outputs will remain low, thus ensuring no glitches on the output. the device monitors both dcs0 and dcs1 inputs and will gate the qn outputs from changing states when both dcs0 and dcs1 are high. if either dcs0 or dcs1 input is low, the qn outputs will function normally. the reset input has priority over the dcs0 and dcs1 control and will force the qn outputs low and the ptyerr output high. if the dcs-control functionality is not desired, then the csgateenable input can be hardwired to ground, in which case, the setup-time requirement for dcs would be the same as for the other d data inputs. the icssstu32871a includes a parity checking function. the ICSSSTUB32871A accepts a parity bit from the memory controller at its input pin parin, compares it with the data received on the d-inputs and indicates whether a parity error has occurred on its open-drain ptyerr pin (active low). package options include 96-ball thin profile fine pitch bga (tfbga, mo-tbd). inputs output reset dcs0 dcs1 ck ck of inputs = h (d0-d21) parin* ptyerr** h lh even l h h lh odd l l hlh even h l h lh odd h h h hl even l h hhl odd l l h hl even h l h hl odd h h h hh xx ptyerr 0 ptyerr 0 h x x l or h l or h x x l x or floating x or floating x or floating x or floating x or floating x or floating h * parin arrives one clock cycle after the data to which it applies. ** this transition assumes ptyerr is high at the crossing of ck going high and ck going low. if ptyerr is low, it stays latched low for two clock cycles or until reset is driven low .
4 1186g?04/16/07 ICSSSTUB32871A ball assignment signal group signal name type description ungated inputs dcke0, dcke1, dodt0, dodt1 sstl_18 dram function pins not associated with chip select. chip select gated inputs d0 ... d20 sstl_18 dram inputs, re-driven only when chip select is low. chip select inputs dcs0 , dcs1 sstl_18 dram chip select signals. these pins initiate dram address/command decodes, and as such at least one will be low when a valid address/command is present. the register can be programmed to re-drive all d-inputs only (csgateen high) when at least one chip select input is low. re-driven outputs q0...q20, qcs 0-1, qcke0-1, qodt0-1 sstl_18 outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. parity input parin sstl_18 input parity is received on pin parin and should maintain odd parity across the d0...d20 inputs, at the rising edge of the clock. parity error output ptyerr open drain when low, this output indicates that a parity error was identified associated with the address and/or command inputs. ptyerr will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard ddr-ii register with parity (in jedec definition). program inputs csgateen 1.8 v lvcmos chip select gate enable. when high, the d0..d20 inputs will be latched only when at least one chip select input is low during the rising edge of the clock. when low, the d0...d20 inputs will be latched and redriven on every rising edge of the clock. clock inputs ck, ck sstl_18 differential master clock input pair to the register. the register operation is triggered by a rising edge on the positive clock input (ck). miscellaneous inputs reset 1.8 v lvcmos asynchronous reset input. when low, it causes a reset of the internal latches, thereby forcing the outputs low. reset also resets the ptyerr signal. vref 0.9 v nominal input reference voltage for the sstl_18 inputs. two pins (internally tied together) are used for increased reliability .
5 1186g?04/16/07 ICSSSTUB32871A block diagram dq r dq r dq r dq r dq r dq r dq r parin d0 d20 vref (cs active) dcs0 dcs1 dcke0, dcke1 dodt0, dodt1 csgateen reset ck ck 21 pa r i t y generator and checker q0 q20 qcs0 qcs1 qcke0, qcke1 qodt0, qodt1 ptyerr 2 2 2 2
6 1186g?04/16/07 ICSSSTUB32871A parity functionality block diagram d 21 d d latching and reset function see note (1) ptyerr d qn dn parin clock q 002aaa417 21 (1) this function holds the error for two cycles. see functional description and timing diagram.
7 1186g?04/16/07 ICSSSTUB32871A register timing ck dn (1) qn t su ck n n + 1 n + 2 n + 3 n + 4 dcsn reset t act t h t pdm , t pdmss ck to q parin t su t h t phl , t plh ck to ptyerr t phl ck to ptyerr ptyerr h, l, or x h or l (1) after reset is switched from low to high, all data and parin input signals must be set and held low for a minimum time of t (max) to avoid false error. act figure 4 reset switches from l to h ?
8 1186g?04/16/07 ICSSSTUB32871A register timing figure 5 ? reset being held high ck dn (1) qn t su 002aaa984 ck n n + 1 n + 2 n + 3 n + 4 dcsn reset t h t pdm , t pdmss ck to q parin t h t phl , t plh ck to ptyerr ptyerr output signal is dependent on the pr ior unknown event h or l unknown input e vent t su
9 1186g?04/16/07 ICSSSTUB32871A register timing figure 6 ? reset ck (1) dcsn reset t inact t rphl reset to q pa r i n (1) t rplh reset to ptyerr ptyerr h, l, or x h or l ck (1) dn (1) qn switches from h to l (1) after reset is switched from high to low, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of t (max) inact
10 1186g?04/16/07 ICSSSTUB32871A absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 2.5v input voltage 1, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vdd +2.5v output voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vddq + 0.5v input clamp current . . . . . . . . . . . . . . . . . . . . 50 ma output clamp current . . . . . . . . . . . . . . . . . . . 50ma continuous output current . . . . . . . . . . . . . . . 50ma vdd or gnd current/pin . . . . . . . . . . . . . . . . 100ma package thermal impedance 3 . . . . . . . . . . . . . . . 36c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this value is limited to 2.5v maximum. 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions parameter min typ max units v ddq 1.7 1.8 1.9 v ref 0.49 x v dd 0.5 x v dd 0.51 x v dd v tt v ref - 0.04 v ref v ref + 0.04 v i input voltage 0 v ddq v ih ( dc ) dc input high voltage v ref + 0.125 v ih ( ac ) ac input high voltage v ref + 0.250 v il ( dc ) dc input low voltage v ref - 0.125 v il ( ac ) ac input low voltage v ref - 0.250 v ih input high voltage level 0.65 x v ddq v il input low voltage level 0.35 x v ddq v icr common mode input range 0.675 1.125 v id differential input voltage 0.600 i oh -8 i ol 8 t a 070c 1 guaranteed by design, not 100% tested in production. ma note: rst and cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless rst is low. v description i/o supply voltage reference voltage operating free-air temperature reset ck, ck low-level output current termination voltage high-level output current data inputs
11 1186g?04/16/07 ICSSSTUB32871A output buffer characteristics output edge rates over recommended operating free-air temperature range (see figure 7) min max dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt_ 1 1v/ns 1. difference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate) parameter v dd = 1.8v 0.1v unit electrical characteristics - dc t a = 0 - 70c; v dd = 2.5 +/-0.2v, v ddq =2.5 +/-0.2v; (unless otherwise stated) symbol parameters v ddq min typ max units v oh i oh = -8ma 1.7v 1.2 v ol i ol = 8ma 1.7v 0.5 i i all inputs v i = v d d or gnd 1.9v 5 a standby (static) r eset = gnd 200 a operating (static) v i = v ih(ac) or v il(ac) , reset = v d d 150 ma dynamic operating (clock only) reset = v dd ,v i = v ih(ac) or v il(ac) , clk and clk switching 50% duty cycle. tbd a/clock mhz dynamic operating (per each data input) reset = v dd , v i = v ih(ac) or v il (ac) , clk and clk switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle tbd a/ clock mhz/data data inputs 2.5 5 clk and clk 2 3.8 reset 4.5 pf notes: 1 - guaranteed by design, not 100% tested in production. c i v i = v ddq or gnd i dd i ddd i o = 0 conditions v i = v ref 350mv v ic r = 1.25v, v i ( pp ) = 360mv pf v 1.8v 1.9v
12 1186g?04/16/07 ICSSSTUB32871A switching characteristics (over recommended operating free-air temperature range, unless otherwise noted) symbol parameter measurement conditions min max units fmax max input clock frequency 410 mhz t pdm propagation delay, single bit switching clk and clk to qn 1.25 1.9 ns t lh low to high propagation delay clk and clk to p tyer r 1.2 3 ns t hl high to low propagation delay clk and clk to p tyer r 0.9 3 ns t pdmss propagation delay simultaneous switching clk and clk to qn 2 ns t phl high to low propagation delay reset to qn 3ns t plh low to high propagation delay reset to ptyerr 3ns 1. guaranteed by design, not 100% tested in production. timing requirements (over recommended operating free-air temperature range, unless otherwise noted) min max f clock clock frequency 410 mhz t w pulse duration 1 ns t act differential inputs active time 10 ns t inact differential inputs inactive time 15 ns t s data before clk , clk 0.6 dcs0 , dsc1 before clk , c lk , c s r high 0.7 hold time dcs , dodt, dcke and dn after clk , c lk 0.6 ns hold time par_in after clk , clk 0.5 ns 1 - guaranteed by design, not 100% tested in production. 2 - for data signal input slew rate of 1v/ns. 4 - clk/ c lk signal input slew rate of 1v/ns. symbol notes: t h 3 - for data signal input slew rate of 0.5v/ns and < 1v/ns. v dd = 1.8v 0.1v units parameters ns setup time
13 1186g?04/16/07 ICSSSTUB32871A notes: 1. c l incluces probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma. 3. all input pulses are supplied by generators having the following chareacteristics: prr 10 mhz, zo=50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v ref = v dd /2 6. v ih = v ref + 250 mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600 mv 9. t plh and t phl are the same as t pdm . r l = 1000 c l = 30 pf (see note 1) load circuit t w v icr v icr inpu t v ih v il voltage waveforms ? pulse duration v ref v ref inpu t t su t h v id v icr voltage waveforms ? setup and hold times v icr v id v icr output v ol v oh v tt v tt t phl t plh voltage waveforms ? propagation delay times t rphl v ol v oh v il v ih output voltage waveforms ? propagation delay times v dd /2 v tt t act t inact lv cmos input rst voltage and current waveforms i dd (see note 2) 90% 10% inputs active and inactive times 0 v v dd tes t po i n t v dd /2 v dd /2 vcmos inp ut rst tl=350ps, 50 dut ck out tl=50 ck inputs v id ck ck ck ck r l = 100 ck tes t po i n t tes t po i n t r l = 1000 v dd figure 6 parameter measurement information (v = 1.8v 0.1v) ? dd
14 1186g?04/16/07 ICSSSTUB32871A notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). c l = 10 pf (see note 1) load circuit ? high-to-low slew-rate measurement tes t po i n t dut out dt_f v ol v oh voltage waveforms ? high-to-low slew-rate measurement 80% output 20% dv_f r l = 50 c l = 10 pf (see note 1) load circuit ? low-to-high slew-rate measurement tes t po i n t dut out dt_r v ol v oh voltage waveforms ? low-to-high slew-rate measurement 80% output 20% dv _r r l = 50 v dd figure 7 output slew-rate measurement information (v = 1.8v 0.1v) dd ?
15 1186g?04/16/07 ICSSSTUB32871A 3 test circuits and switching waveforms (cont?d) 3.3 error output load circuit and voltage measurement information (v dd =1.8v0.1v) all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o = 50 ; input slew rate = 1 v/ns 20%, unless otherwise specified. (1) c l includes probe and jig capacitance. figure 28 ? load circuit, error output measurements ? ? ? c l = 10 pf (see note 1) load circuit ? high-to-low slew-rate measurement test point dut out r l = 1k v dd lvcmos rst input plh t output waveform 2 cc v/2 0.15 v cc v 0 v oh v 0 v figure 29 voltage waveforms, open-drain output low-to-high transition time with respect to reset input timing inputs output waveform 1 phl t icr v cc v /2 icr v v i (pp) cc v ol v timing inputs output waveform 2 phl t icr v icr v v i (pp) oh v v 0 0.15 v voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs figure 30 voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs figure 31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
16 1186g?04/16/07 ICSSSTUB32871A 3 test circuits and switching waveforms (cont?d) 3.4 partial-parity-out load circuit and voltage measurement information (v dd =1.8v0.1v) all input pulses are supplied by generators having the following characteristics: prr 10 mhz; z o = 50 ; input slew rate = 1 v/ns 20%, unless otherwise specified. (1) c l includes probe and jig capacitance. figure 32 ? partial-parity-out load circuit, v tt = v dd /2 t plh and t phl are the same as t pd . v i(pp) = 600 mv figure 33 ? partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs v tt = v dd /2 t plh and t phl are the same as t pd . v ih = v ref + 250 mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos inputs. v il = v ref - 250 mv (ac voltage levels) for differential inputs. v il = v dd for lvcmos inputs. figure 34 ? partial-parity-out voltage waveforms; pr opagation delay times with respect to reset input v oh v ol output t plh 002aaa375 v tt v icr v icr t phl ck ck v i(p-p) t phl 002aaa376 lvcmos rst input output v tt v dd /2 v ih v il v oh v ol dut out test point r l = c l = 5 pf (see note a) 1 k
17 1186g?04/16/07 ICSSSTUB32871A ordering information ICSSSTUB32871Az(lf)t - e - typ b ref b ref alpha designations for vertical grid (letters i, o, q & s not used) alpha designations for vertical grid (letters i, o, q & s not used) numeric designations for horizontal grid numeric designations for horizontal grid h typ h typ c ref c ref a b c d top view a1 3 2 1 4 seating plane seating plane c t 0.12 c d typ e d d1 d1 d1 d1 d1 - e - - e - - e - e1 typ typ example: designation for tape and reel packaging lead free, rohs compliant (optional) package type h = lfbga (reduced size: 5.5 x 13.50) hm = tfbga (reduced size: 5.0 x 11.50) revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y z (lf) t d e t e horiz vert total d h b c min/max min/max min/max 13.50 bsc 5.50 bsc 1.20/1.40 0.80 bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75 11.50 bsc 5.00 bsc 1.00/1.20 0.65 bsc 6 16 96 0.35/0.45 0.25/0.35 0.875 0.875 mo-205 10-0055c * source ref.: jedec publication 95, all dimensions in millimeters ref. dimensions ----- ball grid ----- max. note: ball grid total indicates maximum ball count for package. lesser quantity may be used.
18 1186g?04/16/07 ICSSSTUB32871A revision history rev. issue date description page # b 3/20/2006 updated ordering information. 17 c 2/2/2007 applications, 2nd bullet, changed ulp877 to ulpa877a, added idtcspua877a 1 d 3/1/2007 page 1, applications, 3rd bullet, removed 800; page 11, electrical table, changed idd operating max from 80 to 150, changed reset typ from 2.5 to 4.5; page 12, timing table, changed ts (data before ...) from 0.5 to 0.6, changed th ( d cs , dodt...) from 0.5 t 1, 11, 12 e 3/6/2007 timing table, th hold time, changed q to dn; switching cha. table, fixed typos. 12 f 3/13/2007 page 1, recc. list, changed 3rd bullet to "provides complete ddr dimm solution with ics98ulpa877a, ics97ulp877, or idtcspua877a"; page 11, fixed typos. 1, 11 g 4/16/2007 electrical cha. table, changed ci: data inputs max from 3.5 to 5, and clk max from 3 to 3.8. 11

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